1. Field of the Invention
The present invention relates to a method of fabricating multilevel interconnects of semiconductor devices, and more particularly, to a method of fabricating a dual damascene structure.
2. Description of Related Art
Due to the higher and higher integration of semiconductor devices within integrated circuits (IC), there is not enough area to place and fabricate the needed interconnects. In accordance with the need for an increased number on interconnects on downsized metal oxide semiconductor (MOS) transistors, it has become necessary to include two or more metal layers in IC fabrication design. Usually, the metal layers are separated with inter-metal dielectric (IMD), wherein the conducting lines for connecting two separated metal layers is a so-called `via plug`.
There are two conventional methods of fabricating via holes and interconnects. The first method includes two steps: forming a dielectric layer on the top of a metal layer, followed by defining, a photoresist layer on the top the dielectric layer, then finishing up a via by etching; and forming a via plug by depositing conducting material into the via, defining a metal layer after depositing the metal layer, then, finally, depositing the IMD. The second method applies the technique of a dual damascene structure to form via holes and inter-connects simultaneously. However, the conventional dual damascene structure technique results in smaller via areas, or furthermore the loss of material from the silicon nitride (SiN) layer, because of the comparatively large deviation of the etching critical dimension. Therefore, the present invention is to overcome the drawback of conventional dual damascene structure technique.
FIGS. 1A through 1F show a conventional fabricating technique for a dual damascene structure in sequence. As shown in FIG. 1A, the MOS device, the substrate 10, is not shown completely, the conductive region 12 can be used as either a drain or a source within a transistor, a metal layer within a gate structure, or a metal layer within an inter-connect. First, IMD layer 14 is formed on the substrate and then etching stop layer 16 is formed over IMD layer 14. IMD layer 14 can be, for example, SiO.sub.2, and etching stop layer 16 can be, for example, silicon nitride with a thickness of about 1000 to 2000 .ANG.. Then, a predetermined photoresist layer 18 is formed on etching stop layer 16. The region for forming the via hole is now defined on the photoresist 18.
Next, in FIG. 1B, the photoresist 18 serves as a mask, through which a dry etching is performed on the SiN, forming a hole 17 in the etching stop layer 16a to expose the dielectric layer 14. The photoresist 18 is then removed.
In FIG. 1C, another layer of IMD 24 is formed above the substrate 10. Then, as shown in FIG. 1D, a predetermined photoresist 28 is formed on the top of IMD layer 24 to expose the regions intended to be interconnects. Referring to FIG. 1E, after the high SiO.sub.2 /SiN etching selectivity dry etching is performed on the desired regions of the IMD layer (the IMD 24, as shown in FIG. 1D) by using the photoresist 28 as the ask, two interconnect holes 25 and 35 are formed, and a via hole 15 is formed in IMD layer 14a as well. Part of the etching stop layer 16b and part of the conductive region 12 are also both exposed.
An etching process of a very high SiO.sub.2 /SiN etching selectivity is employed in the conventional method in order to prevent a short between the interconnect and the underlying conductive layer due to etching through. Such a short occurs because of an unstable thickness of the interconnect, occurring on the SiN layer under the interconnect hole 35 during the process of etching the via hole 15 following the etching process of interconnect holes 25 and 35. However, an etching process with a very high SiO.sub.2 /SiN etching selectivity usually forms via holes lacking the desired degree of verticality, which reduces the bottom area of via hole 15 so that contact resistance is increased.
As shown in FIG. 1F, after the photoresist is removed, a glue/barrier layer 20, conforming to via hole 15, interconnect hole 25, and the sidewalls of the interconnect hole 35, is deposited in order to increase adherence between the subsequently deposited metal layer and other material. A metal layer 30 is deposited into via hole 15, interconnect hole 25 and 35, and on IMD layer 24a. The portions of metal layer 30 lying on the upper surface of IMD 24a are then removed by chemical mechanical polishing (CMP), to expose IMD 24a. This concludes the fabrication of a dual damascene structure.
The conventional dual damascene structure technique is a technique to form a via and interconnect at the same time by employing a very high SiO.sub.2 /SiN etching selectivity. However, the bottom area of the via hole decreases gradually as it gets close to the conductive region, which leads to a higher contact resistance. When the depth of the via hole increases, its bottom area decreases correspondingly. If the conductive region is small as well, it is easy to make the contact resistance between the via hole and conducting region get higher.